Some conventional computing systems employ a non-volatile memory device, such as, a not AND or NAND logic-gate based flash memory together with a volatile random access memory (RAM) to reduce write operation latency for write operations from a host application. NAND-type flash memory has been deployed in main memories, memory cards, universal serial bus (USB) flash drives, and solid-state drives for general storage and in some designs to facilitate the transfer of data between devices. Other examples of non-volatile memory include read-only memory (ROM), ferro-electric RAM (F-RAM), magnetic computer storage devices (including hard disk drives, floppy disks, and magnetic tape), optical disks and early data storage methods such as paper tape and punched cards.
FIG. 1 illustrates an implementation of such a conventional storage system 10 supported by a host computer 12 and data storage elements in a host bus adapter (HBA) 20. The central processor unit (CPU) 14 of the host computer 12 accesses a volatile RAM 22 via a memory bus or a standard input/output (I/O) bus 15 for peripheral devices (e.g., the peripheral component interconnect express (PCIe)). A power supply (not shown) coupled to the HBA 20 may be supplemented by a battery or batteries that are available to power the HBA 20 in case the AC power is interrupted to the power supply. The battery or batteries ensure that HBA 20 has sufficient time to transfer data in the volatile RAM 22 to a non-volatile storage element 26. Once power has been restored to the HBA 20, the information stored in the non-volatile storage element 26 can be copied or moved into the volatile RAM 22.
The HBA 20 further includes a direct memory access (DMA) engine 24 that allows the microcontroller 28 to access system memory (i.e., one or both of the RAM 22 and the non-volatile storage element 26) independent of the CPU 14. In some embodiments, the microcontroller 28 enables or controls data transfers via an interface 29 to and from one or more data volume(s) 30 stored in a redundant array of independent disks (RAID). An application, executing in the host computer's CPU 14, accesses the RAM 22 in the HBA 20 in accordance with a standard operating system process that maps or associates a host memory address to a physical address in the RAM 22.
FIG. 2 illustrates a conventional memory managed environment 40 illustrating relationships between a virtual address space 50, a page table 62, and pages 72a-72h stored in the RAM 22. The set of all memory addresses in the operating system executing on the host computer 12 identifies an address space. In the illustrated arrangement, a virtual address space 50 includes a set of regions 52a-52h identified by an initial address X and a region offset.
As illustrated, a memory management unit (MMU) 60 generates and manages the page table 62. The page table 62 includes a location identifier or a page identifier 64a-64h and a corresponding indicator or flag 66a-66h. The indicator or flag 66a-66h identifies whether valid data is present at the corresponding location or region 72a-72h of storage addresses in the RAM 22. Once the relationships between entries in the page table 62 are established with the pages 72a-72h stored in the RAM 22, the RAM 22 is “mapped” to the virtual address space 50 and the information stored therein is available for direct access by an application executing on the host computer 12. Such direct accesses are known to boost performance for relatively small write operations to the RAM 22.
The described RAM access methodology functions well when a translation is available for an application identified virtual address and when application memory requirements are smaller than the capacity available in the DRAM. However, there are circumstances where application memory requirements cannot be supported in the available RAM. When faced with such a situation, RAM capacity can be increased until a maximum capacity supported by the storage device design is reached. Although a system design may support additional RAM, such an addition of storage capacity may not be desirable in the light of the increase in procurement costs and later operational costs due to increased power demands on the data storage device. RAM capacity can also be restricted by addressable storage constraints introduced by the basic input/output system (BIOS) installed in the firmware of the host computer.
It would be desirable to provide an improved system and method for processing information without compromising the performance benefit associated with the use of a combination of volatile and non-volatile storage elements in a data store.